1. Field of the Invention
The present invention relates to analog-to-digital converters and, more particularly, to compensation of analog-to-digital converters and associated methods.
2. Description of Related Art
An analog-to-digital converter (ADC), such as used in digital radio receiver applications, often needs to meet a requirement of having a very high spurious-free dynamic range (SFDR), typically greater than 100 dB. Current ADC devices attempt to come close to this requirement with compensation applied internally to the ADC. This results in an SFDR of about 90 to 100 dB. Additional increases in SFDR also have attempted to be achieved by external application of a compensating signal to the ADC output and have seen an improvement of about 10 to 15 dB. External compensation is often done with the use of a look-up table of error values.
For example, FIG. 1 illustrates a prior art ADC external compensation circuit. In normal operation, a desired analog signal 9 is provided as an input to an ADC 10, along with a sampling clock or timing signal 11. The output of the ADC 10 is both delayed by a delay 12 to provide state samples x and differentiated by a differentiator 14 to provide slope samples x′. The state and slope samples x, x′ are provided to an address location 16 of an error-table stored in a random access memory (RAM) device 15. The RAM device 15 produces error compensation samples e from a data port 17 of the RAM device. The state samples x are also provided to a first register 18, and the error compensation samples e are provided to a second register 19 as shown. The error compensation samples e then are subtracted from the ADC output at the correct sampling time 11 at a combiner 20 to provide a compensated ADC output 25. Applicant, however, has recognized that this prior art ADC external compensation circuit is based only on the values residing in the look-up error-table of the RAM device 15 and is not responsive to dynamically changing environmental conditions that characterize given applications, such as an actual digital radio receiver environment, encompassing not only the ADC itself, but all of the components preceding it as well.
Some other prior error-table ADC compensation techniques have been attempted which produce a state—state or a state-slope sample pair to address an error look-up table to get a corresponding error value to apply to the ADC output. Some of these techniques “estimate” the calibrating signal input to the ADC and computes the error. It, however, can be difficult to “estimate” the calibrating input signal, and an imprecise “estimate” of the input signal results in an imprecise estimate of the error.
Others of these techniques compute the error using a linear combination of basis functions where the weighting coefficients are computed in the frequency domain. These other techniques are more direct in attacking the elimination of the described spurious components by computing weighting coefficients in an attempt to minimize the error between the spurious frequency components of the calibration signals and the frequency components of the errors computed by the linear combination of the weights and the basis functions. The result can be an improvement in SFDR by about 10 to 15 dB. Many frequency components remain, however, and these other techniques result only in average behavior. Although errors computed by the basis function can be good in the vicinity of the calibration signal samples, the results tend to diverge away from these samples when error values are needed for other parts of the error-table.
Accordingly, Applicant has recognized that there remains a need for real time ADC compensation and a need to periodically refresh an error-table with up-to-date compensation data based on present environmental conditions directly and indirectly related to the ADC's operation and performance. There is also a need to further reduce or compensate for remaining frequency components in ADC compensation and for ADC compensation that produces better than average results.